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S6 — Run the tiling spike on the reference tablet; FR-DSP-2 stands as written until it does #23

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opened 2026-09-05 16:20:12 +00:00 by dtourolle · 2 comments
dtourolle commented 2026-09-05 16:20:12 +00:00
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Spike S6 — a tiled pipeline on a mid-range Android device with an image larger than available GPU memory. Never run, and it settles two requirements at once.

What it decides

FR-DSP-2 — Tiled computation. architecture.md §6.2 calls for tiling "from day one" on the grounds that retrofitting it is a rewrite. It was not built, and the evidence has since moved against it:

  • core/dr-gpu/tests/frame_budget.rs carries the argument in its own header — one fused dispatch over a viewport-sized target is comfortably inside the frame budget, and "if that stops being true, the recommendation to strike tiled computation from the interactive path stops being supported, and this test is what says so."
  • technical-debt.md TD-4 reaches the same place from the other direction: a tiled convolution at clarity's radius reads nearly twice the taps an untiled one does. The stage that looks most like it wants a tile cache is the one a tile cache would hurt most.

So the open question is not "when is tiling built" but "is FR-DSP-2 still a requirement". Both measurements are about the interactive path. Neither says anything about the export path or a device under memory pressure — which is where the case for tiling actually lives.

NFR-RES-2 — images larger than GPU memory. No answer, and §4.3 knows it: the requirement text asks the reader to "decide explicitly" how ARCH §6.4 and NFR-RES-2 are reconciled. There is no headroom budget, no allocation-failure fallback, and no spill.

What exists already

DetailPass::radius is documented as the halo a tile would have to be grown by, with a test pinning it, and there is no scheduler to read it. Deliberate plumbing, not an oversight — so the spike is not starting from nothing.

Blocked on

Nothing. It needs a device and a large image.

Outcome

Either FR-DSP-2 is struck from the interactive path and restated for export, or the frame-budget recommendation is withdrawn. Record whichever in requirements.md.

See docs/outstanding.md §4.

**Spike S6 — a tiled pipeline on a mid-range Android device with an image larger than available GPU memory.** Never run, and it settles two requirements at once. ## What it decides **FR-DSP-2 — Tiled computation.** `architecture.md` §6.2 calls for tiling "from day one" on the grounds that retrofitting it is a rewrite. It was not built, and **the evidence has since moved against it**: - `core/dr-gpu/tests/frame_budget.rs` carries the argument in its own header — one fused dispatch over a viewport-sized target is comfortably inside the frame budget, and "if that stops being true, the recommendation to strike tiled computation from the interactive path stops being supported, and this test is what says so." - `technical-debt.md` TD-4 reaches the same place from the other direction: a tiled convolution at clarity's radius reads nearly twice the taps an untiled one does. The stage that looks most like it wants a tile cache is the one a tile cache would hurt most. So the open question is **not "when is tiling built" but "is FR-DSP-2 still a requirement"**. Both measurements are about the *interactive* path. Neither says anything about the export path or a device under memory pressure — which is where the case for tiling actually lives. **NFR-RES-2 — images larger than GPU memory.** No answer, and §4.3 knows it: the requirement text asks the reader to "decide explicitly" how ARCH §6.4 and NFR-RES-2 are reconciled. There is no headroom budget, no allocation-failure fallback, and no spill. ## What exists already `DetailPass::radius` is documented as the halo a tile would have to be grown by, with a test pinning it, and there is no scheduler to read it. **Deliberate plumbing, not an oversight** — so the spike is not starting from nothing. ## Blocked on Nothing. It needs a device and a large image. ## Outcome Either FR-DSP-2 is struck from the interactive path and restated for export, or the frame-budget recommendation is withdrawn. Record whichever in `requirements.md`. See `docs/outstanding.md` §4.
dtourolle added the unmet-requirementsize:Mgpuperformancespike labels 2026-09-05 16:20:12 +00:00
dtourolle commented 2026-09-05 16:20:51 +00:00
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Settles FR-DSP-2 and NFR-RES-2 together — they are one measurement, not two.
Related #24: progressive refinement is the cheaper half of the same problem, and #47, which needs the same class of device.

**Settles** FR-DSP-2 and NFR-RES-2 together — they are one measurement, not two. **Related** #24: progressive refinement is the cheaper half of the same problem, and #47, which needs the same class of device.
dtourolle changed title from S6 — Run the tiling spike; it settles FR-DSP-2 and NFR-RES-2 to S6 — Run the tiling spike on the reference tablet; FR-DSP-2 stands as written until it does 2026-09-19 10:19:46 +00:00
dtourolle commented 2026-09-19 10:19:47 +00:00
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Decided 2026-09-19 (be605c0): FR-DSP-2 is kept as written until S6 has run on a mid-range Android device, because frame-budget.md's argument against tiling is a desktop measurement and the clause exists for the device whose memory the image exceeds. NFR-R8 is decided separately (266a5d3): no CPU pipeline, so NFR-RES-2's remaining question is headroom and staging, which S6 also informs. Reference device is now stated in NFR-COMPAT-1: HONOR ROD2-W09.

Decided 2026-09-19 (be605c0): FR-DSP-2 is kept as written until S6 has run on a mid-range Android device, because frame-budget.md's argument against tiling is a desktop measurement and the clause exists for the device whose memory the image exceeds. NFR-R8 is decided separately (266a5d3): no CPU pipeline, so NFR-RES-2's remaining question is headroom and staging, which S6 also informs. Reference device is now stated in NFR-COMPAT-1: HONOR ROD2-W09.
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Reference: dtourolle/DarkRoom#23